What is a Sequence Generator and Its Working

The object of a sequence generator makes simple to include a series of integer values to your dataflow. These series can begin with any digit & have any step. For instance, the series is 40, 45, 50, 55, etc. A series has a similar name as the object of the Sequence Generator. Thus every object of the sequence generator can include simply one series allocated to it. Centerprise creates a series at run time of dataflow known as in-memory series; otherwise, it reads series control data from a table of the database once your dataflow is performed.

In the case of an in-memory sequence, a sequence constantly begins at the “Start Value” that is given in the series properties. In the database sequence case, the previous value which is used can be recorded into the database of control. The latest start value can be used every time once the sequence is raised. So that it generates ever-rising values for the series every time when the dataflow runs. As a result, this series can be noticed like series chain including non-overlapping values.

What is a Sequence Generator?

Definition: A sequence generator is one kind of digital logic circuit. The main function of this is to generate a set of outputs. Every output is one of a number of binary or Q-ary logic levels or symbols. The length of the series may be indefinite otherwise fixed. A special kind of sequence generator is a binary counter. These generators are utilized in a wide variety of applications like coding & control.

Why Sequence Generator is Required?

The sequence generator circuit is used to generate a prescribed series of bits in synchronization through a CLK. This kind of generator is used as a code generator, counters, random bit generators, sequence, and prescribed period generator. The basic design diagram of this is shown below.

The N-bit shift register outputs like Q0 through QN-1 are applied like the inputs to a combinational circuit is known as the next state decoder. Here, the output of a next state decoder ‘Y’ is given as the serial input to the shift register. The designing of the next state decoder is done based on the sequence required.

Sequence Generator using Counters

The sequence generator block diagram using a counter is illustrated below. Here, the combinational circuit is the next state decoder. The input of this state decoder can be obtained from the outputs of the FFs. Similarly, the outputs of this state decoder are given as inputs to the flip-flops. Based on the number of FFs, the required sequence like 0’s or 1’s can be given and this can be generated like 1011011.

The number of flip flops can be decided through the given sequence like the following.

• First, count the number of zeros and ones in the given sequence.
• Select the high number of the two. And let this number will be ‘N’.
• The no. of flip flops can be calculated as N = 2n-1
• For instance, the given sequence is 1011011, where the number of ones is 5 and the number of zeros is two. So choose a higher one from them that is 5. So 5 = 2n-1, so n=4 FFs will be necessary.

Properties

The sequence generator properties include the following.

• Use Shared Sequence
• Reset
• Increment By
• Number of Cached Values
• End Value
• Cycle Start Value
• Initial Value
• Cycle

Transformation of Sequence Generator

The transformation of this generator is passive so it generates numeric values. This transformation is used to generate exclusive primary values and restore lost primary keys. This transformation includes two o/p ports to connect to different transformations. Its transformation can be created to use in single or multiple mappings. A reusable transformation keeps the reliability of the series in every mapping that utilizes an example of the sequence generator transformation. So this transformation can make reusable so that we can use it in multiple mappings. One can reuse this transformation once you execute numerous loads to a solitary target.

For instance, if anyone has a huge input file, then we can separate it into three sessions which run in parallel by using a transformation so that primary key values can be generated. If we use dissimilar transformations, then the service of integration might produce spare key values. In its place, a reusable sequence generator transformation can be used for all the sessions to give an exclusive value for every target row.

Steps Involved in Designing Sequence Generator using D Flip-Flops

We know the function of a counter that allows an exact number of states in a prearranged sequence. For instance, an up-counter with 3-bit counts 0 to 7 whereas a similar order is upturned in the case of down counter.

There are different ways to design the circuits can using FFs, multiplexers. Here we are designing a sequence generator using D FFs in different steps. Similarly, there are different steps involved in designing a sequence generator using JK Flip-Flops.

Let’s take an example that we aim to design a circuit that moves throughout the states of 0-1-3-2 before doing again the similar pattern. The steps involved throughout this method are as follows.

In Step-1

Firstly, we need to decide the no. of FFs which would be necessary to get our object. In the following example, there are four states which are equal to the 2-bit counter states excluding the order where they transfer. From this, one can estimate the necessity of FFs to be two in order to attain our object.

In Step-2

From the step1, let’s design the state transition table for our sequence generator which is illustrated through the initial four columns in the table. In that, the primary two columns specify the present states and the next states. For example, in the first state of our example is “0 = 00” so it leads to the second state that is next state 1 = “01”.

In Step-3

In the state transition table is extended by including the excitation table of the FFs. In this case, the excitation table of the D flip-flop is the fifth & the sixth columns of the table. For instance, look at the present and next states in the table like 1 & 0 respectively then it results ‘0’ in D1. In the following table, the first two columns represent the present state, the second two columns represent the next states and the last two are inputs of D-FF.

In Step-4

In this step, the Boolean expressions for D0 & D1 can be derived with the help of a K-map. But this example is quite easy; so by using Boolean laws, we can solve for D1 & D0. Therefore

D0 = Q1’Q0’ + Q1’ Q0 = Q1’ (Q0’+Q0) = Q1’(1) = Q1’

D1 = Q1’Q0 + Q1 Q0 = Q0 (Q1’+Q1) = Q0 (1) = Q0

In Step-5

The sequence generator can be designed using the D FFs based on inputs like the following.

In the above circuit, the preferred series is generated depending on the supplied CLK pulses. So it must be noted that the similarity existing here for an easy design can be successfully extended to produce a longer series of bits.

FAQs

1). What is the sequence length in the output of a sequence generator?

The generated output can be of unlimited length or it can be predetermined specified length.

2). What does allocation Size mean to in sequence generator?

The amount of increase when allotting of sequence numbers from the series is termed as allocation Size.

3). How a sequence generator is utilized in Informatica?

It is a connected transformation where the output will be numerical values. The generated keys can be either primary or foreign keys.

Thus, this is comprehensive information on the concept of the Sequence Generator. Know more about the related info such as how sequence generator is implemented in various applications and domains, and how it is operated?