What is RISC V Processor : Architecture, Working & Its Applications

RISC V is an Instruction set architecture developed by the University of California, Berkeley. The concept of RISC was motivated by the truth that most of the processor instructions were not utilized by most computer programs. So, unnecessary decoding logic was being utilized within the designs of processors, consuming more power as well as area. To shorten the instruction set & to invest more within register resources, the RISC V processor was implemented.

This technology was noticed by many tech giants and start-ups because it is completely open source & free. Most types of processors are available with a license agreement, however with this type of processor; anyone can make their new processor designs. So this article discusses an overview of a RISC V processor – working and its applications.

What is RISC V Processor?

In the RISC V processor, the term RISC stands for “reduced instruction set computer” which executes few computer instructions whereas ‘V’ stands for the 5th generation. It is an open-source hardware ISA (instruction set architecture) based on the established principle of RISC.

As compared to other ISA designs, this ISA is available with an open source license. So, a number of manufacturing companies have announced and also provided RISC-V hardware, with open-source operating systems.

This is a new architecture and is available in open, non-restrictive & free licenses. This processor has extensive support from chip & device makers industries. So it is mainly designed to be freely extensible & customizable to use in many applications.

RISC V History

The RISC was invented by Prof. David Patterson around 1980 at the University of California, Berkeley. The Prof. David with Prof. John Hennessy submitted their efforts in two books namely “Computer Organization and Design” & “Computer Architecture at Stanford University. So, they received the ACM A.M. Turing award in the year 2017.

From the year 1980 to the 2010 year, the RISC fifth-generation development research was started and finally came to be identified as RISC-V which is pronounced as risk five.

RISC V Architecture & Working

The RV12 RISC V architecture is shown below. The RV12 is highly configurable with a single-core RV32I and RV64I compliant RISC CPU which is used in embedded fields. The RV12 is also from a 32 or 64-bit CPU family depending on the industrial standard RISC-V instruction set.

The RV12 simply executes a Harvard architecture for simultaneous access to instruction as well as data memory. It also includes a 6-stage pipeline which helps in optimizing overlaps in between the execution as well as memory accesses to improve efficiency. This architecture mainly includes Branch Prediction, Data Cache, Debug Unit, Instruction Cache, & optional Multiplier or Divider Units.

The main features of RV12 RISC V include the following.

• It is an Industry standard instruction set.
• Parameterized with 32 or 64bit data.
• It has precise and fast interrupts.
• Custom instructions allow the addition of proprietary hardware accelerators.
• Execution of single cycle.
• Six-stage pipeline with optimizing folded.
• Support with memory protection.
• Optional or Parameterized caches.
• Extremely Parameterized.
• Users can select 32/ 64-bit data & Branch Prediction Unit.
• Users can select instruction/data caches.
• User selectable structure, size & architecture of cache.
• Hardware Divider or Multiplier Support by user-defined latency.
• The bus architecture is flexible which supports Wishbone & AHB.
• This design optimizes the power & size.
• Design is completely parameterized which provides performance or power tradeoffs.
• Gated CLK design to decrease power.
• Software support by Industry standard.
• Architectural simulator.
• Eclipse IDE is used for Linux/ Windows.

The RISC V Execution Pipeline

It include five stages like IF (instruction fetch), ID (instruction decode), EX (execute), MEM (memory access) & WB (register write-back).

Instruction Fetch

In Instruction Fetch or IF stage, a single instruction is read from the program counter (PC) and instruction memory which is updated to the next instruction.

Instruction Pre-Decode

Once RVC Support is allowed, then the Instruction Pre-Decode stage will decode a 16-bit-compressed instruction into a native 32-bit instruction.

Instruction Decode

In the Instruction Decode (ID) stage, the Register File is allowed & the bypass controls are decided.

Execute

In Execute stage, the result is calculated for an ALU, DIV, MUL instruction, the memory allowed for a Store or Load instruction, and branches & jumps are measured against their expected outcomes.

Memory

In this Memory stage, the memory is accessed through the pipeline. The inclusion of this phase ensures the pipeline’s high performance.

Write Back

In this stage, the Execution stage result is written into the Register File.

Branch Predictor

This processor includes a branch predictor unit or BPU that is used to store past data to guide the RISC V processor in deciding whether a specific branch is taken or not-. This predictor data is simply updated once the branch executes.

This unit includes different parameters which determine its behavior. For example, HAS_BPU is used to determine if a branch predicts a unit is present, BPU_GLOBAL_BITS will determine how many past bits should be used and BPU_LOCAL_BITS will determine how many of the LSB of the program counter should be used. The combination of BPU_LOCAL_BITS & BPU_GLOBAL_BITS will create a vector that is mainly utilized to address the Branch-Prediction-Table.

Data Cache

This is mainly used to speed up the access of data memory by buffering newly accessed locations of memory. This is capable of handling half-word, byte & word accesses when  XLEN = 32 if they are on their own boundaries. It is also capable of handling half-word, byte, word & double-word accesses when XLEN=64 if they are on their own boundaries.

Throughout a cache miss, a whole block can be written back to memory, So if necessary, a new block can be loaded into the cache. The Data Cache is disabled by setting DCACHE_SIZE to zero. After that, memory locations are accessed directly through the Data Interface.

Instruction Cache

This is mainly used to speed up the fetching of instruction by buffering newly fetched instructions. This cache is used to fetch one parcel for each cycle on any 16-bit boundary but not across a block boundary. Throughout a cache miss, a whole block can be loaded from the instruction memory. The configuration of this cache can be done based on the needs of the user. The size of the cache, replacement algorithm, and block length is configurable.

The instruction cycle will be disabled by Setting ICACHE_SIZE to zero. After that, parcels are fetched directly from the memory through the Instruction Interface.

Debug Unit

The Debug Unit will allow the Debug surroundings to stop and examine the CPU. The main features of this are Branch Tracing, Single Step Tracing up to 8- Hardware Breakpoints.

Register File

This is designed with 32 register locations from X0 to X31 where X9 Register is zero always. The Register File includes 1- write port & 2- read ports.

Configurable Interface

This is an external interface where this processor supports different external bus interfaces.

How does RISC V Works?

RISC-V is an instruction set architecture rooted within RISC (reduced instruction set computer) principles. This processor is very unique and also revolutionary as it is a free, common, and open-source ISA where hardware can be developed, the software can be ported & processors can be designed to support it.

Difference B/W RISC V Vs MIPS

The difference between RISC V and MIPS includes the following.

RISC V	MIPS
The term RISC V stands for Reduced Instruction Set Computer where ‘V’ is the fifth generation.	The term “MIPS” stands for “Million instructions per second”.
RISC-V simply permits the manufacturers of smaller devices to design hardware without paying.	MIPS allows the manufacturer to measure the processor’s speed by paying because it is not free.
MIPS is efficiently dead.	RISC-V is not efficiently dead.
This processor provides branch instructions for comparing two registers.	MIPS depends on a comparison instruction that locates a register to 1 or 0 based on whether the contrast is true.
ISA encoding scheme is fixed & variable in RISC V.	ISA encoding scheme is fixed in MIPS
Instruction set size is 16-bit or 32-bit or 64-bit or 128-bit.	The instruction set size is 32-bit or 64-bit.
It has 32 general purpose & floating point registers	It has 31 general purpose & floating point registers.
It has 26-single & double precision floating point operations.	It has 15-single & double precision floating point operations.

Difference B/W RISC V Vs ARM

The difference between RISC V Vs ARM includes the following.

RISC V	ARM
RISC-V is open source, so it doesn’t require any license.	ARM is a closed source, so it needs a license.
It is a new processor platform, so there is very small support for software & programming environments.	ARM has a very large online community, which supports libraries & structures to assist the target designers in various platforms like microprocessors, microcontrollers & also servers.
RISC V-based chips use 1 watt of power.	ARM-based chips use below 4 watts of power.
It has a fixed & variable ISA encoding system.	It has a fixed ISA encoding system.
RISC V instruction set size ranges from 16-bit to 128-bits.	Its instruction size ranges from 16-bit to 64-bits.
It includes 32 general purpose & floating point registers.	It includes 31 general purpose & floating point registers.
It has 26-single precision floating point operations.	It has 33-single precision floating point operations.
It has 26-double precision floating point operations.	It has 29-double precision floating point operations.

RISC V Verilog Code

The instruction memory verilog code for RISC is shown below.

// Verilog code for RISC Processor
// Verilog code for Instruction Memory

module Instruction_Memory(
input[15:0] pc,
output[15:0] instruction
);

reg [`col – 1:0] memory [`row_i – 1:0];
wire [3 : 0] rom_addr = pc[4 : 1];
initial
begin
$readmemb(“./test/test.prog”, memory,0,14);
end
assign instruction = memory[rom_addr];

endmodule

Verilog code for the 16-bit RISC V processor:

module Risc_16_bit(
input clk
);

wire jump,bne,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write;
wire[1:0] alu_op;
wire [3:0] opcode;

// Datapath

Datapath_Unit DU
(
.clk(clk),
.jump(jump),
.beq(beq),
.mem_read(mem_read),
.mem_write(mem_write),
.alu_src(alu_src),
.reg_dst(reg_dst),
.mem_to_reg(mem_to_reg),
.reg_write(reg_write),
.bne(bne),
.alu_op(alu_op),
.opcode(opcode)
);

// control unit
Control_Unit control
(
.opcode(opcode),
.reg_dst(reg_dst),
.mem_to_reg(mem_to_reg),
.alu_op(alu_op),
.jump(jump),
.bne(bne),
.beq(beq),
.mem_read(mem_read),
.mem_write(mem_write),
.alu_src(alu_src),
.reg_write(reg_write)
);
endmodule

Instruction Sets

The RISC V instruction sets are discussed below.

Arithmetic Operations

The RISC V arithmetic operations are listed below.

Mnemonic	Type	Instruction	Description
ADD  rd, rs1, rs2	R	Add	rdß rs1 + rs2
SUB rd, rs1, rs2	R	Subtract	rdß rs1 –  rs2
ADDI rd, rs1, imm12	I	Add immediate	rdß rs1 + imm12
SLT rd, rs1, rs2	R	Set less than	rdß rs1 -< rs2
SLTI rd, rs1, imm12	I	Set less than immediate	rdß rs1 -< imm12
SLTU rd, rs1, rs2	R	Set less than unsigned	rdß rs1 -< rs2
SLTIU rd, rs1, imm12	I	Set less than immediate unsigned	rdß rs1 -< imm12
LUI rd,imm20	U	Load upper immediate	rdß imm20<<12
AUIP rd,imm20	U	Add upper immediate to PC	rdß PC+imm20<<12

 Logical Operations

The RISC V logical operations are listed below.

Mnemonic	Type	Instruction	Description
AND  rd, rs1, rs2	R	AND	rdß rs1 & rs2
OR rd, rs1, rs2	R	OR	rdß rs1 | rs2
XOR  rd, rs1, rs2	R	XOR	rdß rs1 ^  rs2
ANDI  rd, rs1, imm12	I	AND immediate	rdß rs1 & imm2
ORI rd, rs1, imm12	I	OR Immediate	rdß rs1 | imm12
OXRI rd, rs1, imm12	I	XOR immediate	rdß rs1 ^ rs2
SLL rd, rs1, rs2	R	Shift left logical	rdß rs1 <<  rs2
SRL rd, rs1, rs2	R	Shift right logical	rdß rs1 >>  rs2
SRA rd, rs1, rs2	R	Shift right arithmetic	rdß rs1 >>  rs2
SLLI rd, rs1, shamt	I	Shift left logical immediate	rdß rs1 <<  shamt
SRLI rd, rs1, shamt	I	Shift right logical immediate	rdß rs1 >> shamt
SRAI rd, rs1, shamt	I	Shift right arithmetic immediate	rdß rs1 >> shamt

 Load/Store Operations

The RISC V load/store operations are listed below.

Mnemonic	Type	Instruction	Description
LD  rd, imm12 (rs1)	I	Load doubleword	rdß mem [rs1 +imm12]
LW rd, imm12 (rs1)	I	Load word	rdß mem [rs1 +imm12]
LH rd, imm12 (rs1)	I	Load halfword	rdß mem [rs1 +imm12]
LB rd, imm12 (rs1)	I	Load byte	rdß mem [rs1 +imm12]
LWU rd, imm12 (rs1)	I	Load word unsigned	rdß mem [rs1 +imm12]
LHU rd, imm12 (rs1)	I	Load half word unsigned	rdß mem [rs1 +imm12]
LBU rd, imm12 (rs1)	I	Load byte unsigned	rdß mem [rs1 +imm12]
SD  rs2, imm12 (rs1)	S	Store double word	rs2 à mem [rs1 +imm12]
SW rs2, imm12 (rs1)	S	Store word	rs2 (31:0) à mem [rs1 +imm12]
SH rs2, imm12 (rs1)	S	Store halfword	rs2 (15:0) à mem [rs1 +imm12]
SB rs2, imm12 (rs1)	S	Store byte	rs2 (15:0) à mem [rs1 +imm12]
SRAI rd, rs1, shamt	I	Shift right arithmetic immediate	rs2 (7:0) à mem [rs1 +imm12]

Branching Operations

The RISC V branching operations are listed below.

Mnemonic	Type	Instruction	Description
BEQ  rs1, rs2, imm12	SB	Branch equal	If rs1== rs2 PC ß PC+imm12
BNE  rs1, rs2, imm12	SB	Branch not equal	If rs1!= rs2 PC ß PC+imm12
BGE  rs1, rs2, imm12	SB	Branch greater than or equal	If rs1>= rs2 PC ß PC+imm12
BGEU  rs1, rs2, imm12	SB	Branch greater than or equal to unsigned	If rs1>= rs2 PC ß PC+imm12
BLT  rs1, rs2, imm12	SB	Branch less than	If rs1< rs2 PC ß PC+imm12
BLTU  rs1, rs2, imm12	SB	Branch less than  unsigned	If rs1< rs2 PC ß PC+imm12 <<1
JAL  rd, imm20	UJ	Jump and Link	rdßPC+4 PCß PC+imm20
JALR  rd, imm12(rs1)	I	Jump and Link register	rdßPC+4 PCß rs1+imm12

 Advantages

The advantages of the RISC V processor include the following.

• By using RISCV, we can save development time, software development, verification, etc.
• This processor has many pros like simplicity, openness, modularity, clean-slate design, and extensibility.
• This is supported by several language compilers like the GCC (GNU Compiler Collection), a free-software compiler & through the Linux OS.
• This can be used by companies freely due to no royalties, no licensing fees & no strings connected.
• RISC-V processor doesn’t include any new or innovative features because it simply follows established principles of RISC.
• Similar to several other ISAs, this processor specification simply defines various instruction set levels. So this contains 32 & 64-bit variants as well as extensions to give support for floating point instructions.
• These are free, simple, modular, stable, etc.

Disadvantages

The disadvantages of the RISC V processor include the following.

• Complex instructions are frequently used by compilers & programmers.
• The o/p of a RISC may change based on the code when subsequent instructions within a loop depend on the earlier instruction for execution.
• These processors need to save a variety of instructions rapidly, which requires a big cache memory set to respond to the instruction within a timely manner.
• The complete features, capabilities & benefits of RISC mainly depend on the architecture.

Applications

The applications of the RISC V processor include the following.

• RISC-V is used in embedded systems, artificial intelligence & machine learning.
• These processors are used in high-performance-based embedded system applications.
• This processor is appropriate to use in some particular fields like edge computing, AI & storage applications.
• RISC-V is important as it permits smaller device manufacturers to design hardware without paying.
• This processor simply allows the researchers and developers to design as well as research with a freely available ISA or instruction set architecture.
• The applications of RISC V range from small embedded microcontrollers to desktop PCs & supercomputers including vector processors.

Thus, this is an overview of a RISC V Processor – architecture, working with applications. Here is a question for you, what is a CISC processor?