PMOS Transistor : Working, Fabrication, Cross Section & Its Characteristics

The MOS transistor is the most fundamental element in large-scale integrated circuit design. These transistors are generally classified into two types PMOS and NMOS. The combination of NMOS and PMOS transistors is known as a CMOS transistor. The different logic gates & other digital logic devices which are implemented must have PMOS logic. This technology is inexpensive & has good resistance to interference. This article discusses one of the types of MOS transistors like a PMOS transistor.

What is PMOS Transistor?

The PMOS transistor or P-channel metal oxide semiconductor is a kind of transistor where the p-type dopants are utilised in the channel or gate region. This transistor is exactly the reverse of the NMOS Transistor. These transistors have three main terminals; the source, the gate & the drain where the transistor’s source is designed with a p-type substrate, and the drain terminal is designed with an n-type substrate. In this transistor, the charge carriers like holes are responsible for the conduction of current. The PMOS transistor symbols are shown below.

How Does PMOS Transistor Work?

The p-type transistor working is quite opposite to the n-type transistor. This transistor will form an open circuit whenever it gets non-negligible voltage which means, there is no flow of electricity from the gate (G) terminal to the source (S). Similarly, this transistor forms a closed circuit when it gets a voltage at around 0 volts which means the current flows from the gate (G) terminal to the drain (D).

This bubble is also known as an inversion bubble. So the main function of this circle is to invert the input voltage value. If the gate terminal provides a 1 voltage, then this inverter will change it into zero and functions the circuit accordingly. So the function of the PMOS transistor and NMOS transistor is quite opposite. Once we merge them into a single MOS circuit, then it will become a CMOS (complementary metal-oxide semiconductor) circuit.

Cross Section of PMOS Transistor

The cross-section of the PMOS transistor is shown below. A pMOS transistor is built with an n-type body including two p-type semiconductor regions which are adjacent to the gate. This transistor has a controlling gate as shown in the diagram which controls the electrons flow between the two terminals like source & drain. In the pMOS transistor, the body is held at +ve voltage. Once the gate terminal is positive, then the source & drain terminals are reverse-biased. Once this happens, there is no flow of current, so the transistor will be turned OFF.

Once the voltage supply at the gate terminal is lowered, then positive charge carriers will be attracted to the bottom of the Si-SiO2 interface. Whenever the voltage gets low sufficiently then the channel will be inverted and creates a conducting pathway from the source terminal to the drain by allowing the flow of current.

Whenever these transistors deal with digital logic there are usually have two different values only like 1 & 0 (ON and OFF). The transistor’s positive voltage is known as VDD which represents the logic high (1) value within digital circuits. The VDD voltage levels in TTL logic were generally around 5V. At present transistors cannot actually withstand such high voltages because they typically range from 1.5V – 3.3V. The low voltage is frequently known as GND or VSS. So, VSS signifies the logic ‘0’ and it is also set normally to 0V.

PMOS Transistor Circuit

The NAND gate design using the PMOS transistor and NMOS transistor is shown below. Generally, a NAND gate in digital electronics is a logic gate which is also called a NOT-AND gate. The output of this gate is low (0) only if the two inputs are high (1) and its output is a complement to an AND gate. If any of the two inputs are LOW (0), then it gives high output results.

In the below logic circuit, if the input A is 0 and B is 0, then A input of pMOS will produce ‘1’ and A input of nMOS will produce ‘0’. So, this logic gate generates a logical ‘1’ because it is connected to the source by a closed circuit & detached from the GND through an open circuit.

When A is ‘0’ & B” is ‘1’, then A input of pMOS will generate a ‘1’ & A input of NMOS will generate a ‘0’. Thus, this gate will produce a logical one because it is connected to the source through a closed circuit and detached from the GND by an open circuit. When A is ‘1’ & B is ‘0’, then the ‘B’ input of pMOS will generate high output (1) & ‘B’ input of NMOS will generate an output as low (0). So, this logic gate will generate a logical 1 because it is connected to the source through a closed circuit & detached from the GND by an open circuit.

When A is ‘1’ & B is ‘1’, then A input of” pMOS will produce a zero, and A input of nMOS will generate ‘1’. Consequently, we should verify the B input of pMOS & nMOS also. The B input of pMOS will generate a ‘0’ & B input of nMOS will generate a ‘1’. So, this logic gate will generate a logical ‘0’ because it is detached from the source by an open circuit & is connected to the GND through a closed circuit.

Truth Table

The truth table of the above logic circuit is given below.

The threshold voltage of the PMOS Transistor is normally the ‘Vgs’ which is necessary to create the channel known as channel inversion. In a PMOS transistor, the substrate & the source terminals are simply connected to ‘Vdd’. If we start reducing the voltage by reference to the source terminal at gate terminal from Vdd to a point wherever you notice the channel inversion, at this position if you analyze Vgs & source being at the high potential, then you will get a negative value. So, the PMOS transistor has a negative Vth value.

PMOS Fabrication Process

The steps involved in PMOS transistor fabrication are discussed below.

Step1:

A thin silicon wafer layer is changed into N-type material by simply doping phosphorous material.

Step2:

A thick Silicon dioxide (Sio2) layer is grown on a complete p-type substrate.

Step3:

Now the surface is coated with a photoresist over the thick silicon dioxide layer.

Step4:

After that, this layer is simply exposed to UV light through a mask that defines those regions into which diffusion is to take place together with transistor channels.

Step5:

These regions are etched away mutually with the underlying silicon dioxide so that the surface of the wafer is exposed within the window defined by the mask.

Step6:

The remaining photoresist is detached & thin Sio2 layer is grown typically 0.1 micrometers over the entire surface of the chip. After that, polysilicon is placed over this to form the structure of the gate. A photoresist is placed over the whole polysilicon layer & exposes UV light through the mask2.

Step7:

Diffusions are achieved through wafer heating to maximum temperature & passing gas with desired p-type impurities like Boron.

Step8:

A 1-micrometer thickness silicon dioxide is grown & photoresist material is deposited on it. Expose the ultraviolet light with mask3 on the preferred areas of the gate, source & drain which are etched to make the contact cuts.

Step9:

Now a metal or aluminum is deposited over its 1-micrometer thickness surface. Again a photoresist material is grown all over the metal & expose the UV light through mask4 which is etched to form the required interconnection design. The final PMOS structure is shown below.

PMOS Transistor Characteristics

The PMOS transistor I-V characteristics are shown below. These characteristics are divided into two regions in order to obtain the relationship between the drain to source current (I DS) as well as its terminal voltages like linear & saturation regions.

In a liner region, the IDS will linearly increase when the VDS (drain to source voltage) is increased whereas in the saturation region, the I DS is stable & it is independent of VDS. The main relationship between the ISD (source to drain current) & its terminal voltages is derived by a similar procedure of the NMOS transistor. In this case, the only change will be the charge carriers present within the inversion layer are simply holes. When the holes move from source to drain then the flow of current is also the same.

Thus, the negative sign appears within the current equation. In addition, all the applied biases at the terminals of the device are negative. So, the PMOS transistor’s ID – VDS characteristics are shown below.
The drain current equation for PMOS transistor in the linear region is given as :

ID = – mp Cox

Likewise, the Drain current equation for PMOS transistor in the saturation region is given as :

ID = – mp Cox (VSG – | V TH |p )^2

Where ‘mp’ is the hole’s mobility & ‘|VTH| p’ is the PMOS transistor’s threshold voltage.

In the above equation, the negative sign will indicate that the ID( drain current) flows from the drain (D) to the source (S) whereas holes flow in the opposite direction. When the mobility of the hole is low as compared to the electron mobility then PMOS transistors suffer from the capability of the low current drive.

Thus, this is all about an overview of PMOS transistor or p-type mos transistor – fabrication, circuit, and its working. PMOS transistors are designed with a p-source, an n-substrate & drain. The charge carriers of PMOS are holes. This transistor conducts once low voltage is applied at the gate terminal. PMOS-based devices are less prone to interference as compared to NMOS devices. These transistors can be used as voltage-controlled resistors, active loads, current mirrors, trans-impedance amplifiers, and also used in switches and voltage amplifiers. Here is a question for you, what is an NMOS transistor?