NMOS Transistor : Working, Circuit, Fabrication & Its Characteristics

The metal oxide semiconductor transistor or MOS transistor is a basic building block in logic chips, processors & modern digital memories. It is a majority-carrier device, where the current within a conducting channel in between the source & the drain is modulated by an applied voltage to the gate. This MOS transistor plays a key role in various analog & mixed-signal ICs. This transistor is quite adaptable, so functions as an amplifier, a switch, or a resistor. MOS transistors are classified into two types PMOS & NMOS. So, this article discusses an overview of NMOS transistor – fabrication, circuit & working.

What is an NMOS Transistor?

An NMOS (n-channel metal-oxide semiconductor) transistor is one type of transistor where n-type dopants are utilized in the gate region. A positive (+ve) voltage on the gate terminal turns on the device. This transistor is mainly used in CMOS (complementary metal-oxide semiconductor) design & also in logic & memory chips. As compared to the PMOS transistor, this transistor is very faster, so more transistors can be placed on a single chip. The NMOS transistor symbol is shown below.

How Does NMOS Transistor Work?

The working of the NMOS transistor is; when the NMOS transistor receives a non-negligible voltage then it forms a closed circuit which means the connection from the source terminal to the drain works as a wire. So the current flows from the gate terminal to the source. Similarly, when this transistor receives a voltage at approximately 0V then it forms an open circuit which means the connection from the source terminal to the drain will be broken, so current flows from the gate terminal to the drain.

Cross Section of NMOS Transistor

Generally, an NMOS transistor is simply built with a p-type body by two n-type semiconductor regions which are adjacent to the gate known as the source & the drain. This transistor has a controlling gate that controls the electron flow between the source & drain terminals.

In this transistor, since the body of the transistor is grounded, the PN junctions of the source & drain toward the body are reverse-biased. If the voltage at the gate terminal is increased, an electric field will start to increase and attracts free electrons to the base of the Si-SiO2 interface.

Once the voltage is high enough, then electrons wind up filling all the holes & a thin region below the gate known as the channel will get inverted to perform as an n-type semiconductor. This will create a conducting lane from the source terminal to the drain by allowing the flow of current, so the transistor will be turned ON. If the gate terminal is grounded then no current flows in the reverse-biased junction so the transistor will be turned OFF.

NMOS Transistor Circuit

The NOT gate design using PMOS and NMOS transistors is shown below. In order to design a NOT gate, we need to combine pMOS & nMOS transistors by connecting a pMOS transistor to the source & an nMOS transistor to the ground. So circuit will be our first CMOS transistor example.

The NOT gate is one type of logic gate that generates an inverted input as an output. This gate is also called an inverter. If the input is ‘0’, the inverted output will be ‘1’.

When the input is zero, then it goes to the pMOS transistor on top & down to the nMOS transistor at the bottom. Once the input value ‘0’ reaches the pMOS transistor, then it is inverted into ‘1’. thus, the connection toward the source is stopped. So this will generate a logic ‘1’ value if the connection toward the drain (GND) is also closed. We know that the nMOS transistor won’t invert the input value, thus it takes the zero value as it is and it will make an open circuit to the drain. So, a logical one value is generated for the gate.

Similarly, if the input value is ‘1’ then this value is sent to both the transistors in the above circuit. Once the ‘1’ value receives the pMOS transistor, then it will get inverted to an ‘o’. as a result, the connection toward the source is open. Once the nMOS transistor receives the ‘1 value, then it will not get inverted. so, the input value remains as one. Once one value is received by the nMOS transistor, then the connection toward the GND is closed. So it will generate a logic‘0’ as an output.

Fabrication Process

There are many steps involved in the NMOS transistor fabrication process. The same process can be used for PMOS and CMOS transistors. The most frequently used material in this fabrication is either polysilicon or metal. The step-by-step fabrication process steps of the NMOS Transistor are discussed below.

Step1:

A thin silicon wafer layer is changed into P-type material by simply doping with Boron material.

Step2:

A thick Sio2 layer is grown on a complete p-type substrate

Step3:

Now the surface is coated through a photoresist on the thick Sio2 layer.

Step4:

Afterward, this layer is exposed to UV light with a mask that describes those regions into which diffusion is to occur jointly with transistor channels.

Step5:

These regions are etched away mutually with the underlying Sio2 so that the wafer’s surface is exposed within the window defined through the mask.

Step6:

The residual photoresist is separated & thin Sio2 layer is grown 0.1 micrometers typically over the entire face of the chip. Next, polysilicon is located on this to form the gate structure. A photoresist is placed on the complete polysilicon layer & exposes ultraviolet light throughout the mask2.

Step7:

By heating the wafer to the maximum temperature, diffusions are achieved & passing gas with desired n-type impurities like Phosphorous.

Step8:

A one-micrometer thickness of silicon dioxide is grown all over & photoresist material is placed on it. Expose the ultraviolet light (UV) through mask3 on the preferred regions of gate, source & drain regions are etched to make the contact cuts.

Step9:

Now a metal like aluminum is placed over its one-micrometer-width surface. Once more a photoresist material is grown all over the metal & expose to UV light through mask4 which is an etched form to the mandatory interconnection design. The final NMOS structure is shown below.

PMOS Vs NMOS Transistor

The difference between PMOS and NMOS transistors is discussed below.

Characteristics

The I-V characteristics of the NMOS transistor are shown below. The voltage between the gate & the source terminals ‘V_GS’ & also between the source & drain ‘V_DS’. So, the curves between I_DS and V_DS are attained by simply grounding the terminal of the source, setting an initial VGS value & sweeping V_DS from ‘0’ to the highest DC voltage value given by the V_DD when stepping the V_GS value from ‘0’ to V_DD. So for extremely low V_GS, the I_DS are extremely small & will have a linear trend. When the V_GS value gets high, then I_DS enhances & will have the below dependency on V_GS & V_DS;

If V_GS is less than or equal to V_TH, then the transistor is in the OFF condition & performs like an open circuit.

If V_GS is greater than V_TH, then there are two operating modes.

If V_DS is less than V_GS – V_TH, then the transistor works in the linear mode, and performs as a resistance (R_ON).

IDS = u_eff C_ox W/L [(V_GS – V_TH)V_DS – ½ V_DS^2]

Where,

‘µeff’ is the effective mobility of the charge carrier.

‘COX’ is the capacitance of gate oxide for each unit area.

W & L are the width & length of the channel correspondingly. The R_ON value is simply controlled by the voltage of the gate follows as;

R_{ON =}  1/u_nC_ox W/L [(V_GS – V_TH)V_DS – ½ V_DS^2]

If VDS is greater than or equal to V_GS – V_TH, then the transistor works within the saturation mode

I_DS = u_n C_oxW/L [(V_GS – V_TH)^2 (1+λ V_DS]

In this region, when I_DS is higher, then the current is dependent minimally on the V_DS value, however, its highest value is simply controlled through VGS. The channel length modulation ‘λ’ accounts for the raise within IDS by an increase within VDS in transistors, because of pinch-off. This Pinch-off occurs once both V_DS and V_GS decide on the electric field pattern close to the drain region, thus changing the natural supply charge carriers’ direction. This effect cut downs the efficient channel’s length & increases I_DS. Ideally, ‘λ’ is equivalent to ‘0’ so that I_DS is totally independent of the V_DS value within the saturation region.

Thus, this is all about an overview of an NMOS transistor – fabrication and circuit with working. NMOS transistor plays a key role in implementing logic gates as well as other different digital circuits. This is a microelectronic circuit mainly used in the design of logic circuits, memory chips & in CMOS design. The most popular applications of NMOS transistors are switches and voltage amplifiers. Here is a question for you, what is a PMOS transistor?