JTAG : Pin Configuration, Working, Protocol Analyser, Timing Diagram & Its Applications

JTAG (Joint Test Action Group) is a well-established IEEE 1149.1 standard that was developed in the year 1980 to solve the manufacturing issues that occurred within electronic boards or printed circuit boards. This technology is used to provide enough test access for each complex board when test access was decreasing. Thus, boundary scan technology was launched & the JTAG standard or JTAG specification is established. The complexity of electronics has been increasing day by day, so the JTAG specification has become the accepted test format to test complicated & compact electronics units. This article discusses an overview of a JTAG protocol – working with applications.

What is JTAG?

The name which is given to the IEEE 1149.1 Standard Test Access Port as well as Boundary-Scan Architecture is known as JTAG (Joint Test Action Group). This boundary scan architecture is mostly used within computer processors because the first processor with JTAG was released by Intel. This IEEE standard simply defines how the circuitry of a computer is tested to confirm whether it is working correctly after the procedure of manufacturing. On the circuit boards, tests are performed to check the solder joints.

Joint Test Action Group provides a pins-out view for testers with every IC pad which helps in identifying any faults within a circuit board. Once this protocol is interfaced to a chip, this can attach a probe to the chip by allowing a developer to control the chip as well as its connections with other chips. The interface with the Joint Test Action group can also be used by Developers for copying the firmware to non-volatile memory in an electronic device.

Configuration/Pin Out

The Joint Test Action Group includes 20-pins where each pin and its function are discussed below.

Pin1 (VTref): This is the target reference voltage pin that is used to connect to the main power supply of the target which ranges from 1.5 to 5.0VDC.

Pin2 (Vsupply): This is the target supply voltage that is used to connect the main voltage supply of target 1.5VDC – 5.0VDC.

Pin3 (nTRST): This is a test reset pin that is used to reset the state machine of the TAP controller.

Pins (4, 6, 8, 10, 12, 14, 16, 18 & 20): These are common GND pins.

Pin5 (TDI): This is Test Data In the pin. This data is shifted into the target device. This pin must be pulled up on a defined condition on the target board.

Pin7 (TMS): This is the Test Mode State pin that is pulled to determine the next condition of the state machine of the TAP controller.

Pin9 (TCK): This is a test clock pin that synchronizes the internal state machine operations in the TAP controller.

Pin11 (RTCK): This is the Input Return TCK pin that is used in devices that supports adaptive clocking.

Pin13 (TDO): This is the Test Data Out pin, so the data is moved out of the target device into the Flyswatter.

Pin15 (nSRST): This is the Target System Reset pin which is connected to the main reset signal of the target.

Pins 17 & 19 (NC): These are not connected pins.

JTAG Working

The JTAG’s original use is for boundary testing. Here, is a simple printed circuit board including two ICs like CPU & FPGA. A typical board may include many ICs. In general, ICs include many pins which are connected jointly with many connections. Here, in the following diagram, only four connections are shown.

So if you design many boards where every board has thousands of connections. In that, there are some bad boards. So we need to check which board is working and which is not working. For that, the Joint Test Action Group was designed.

This protocol can use the control pins of all the chips but in the following diagram, the Joint Test Action Group is going to make all the output pins of the CPU & all the input pins of FPGA. After that, by transmitting some amount of data from the pins of the CPU & reading the values of the pins from the FPGA, JTAG states that the connections of the PCB board are fine.

Actually, the Joint Test Action Group includes four logic signals TDI, TDO, TMS & TCK. And these signals need to be connected in a particular way. At first, TMS & TCK are connected in parallel to all the ICs of JTAG.

After that, both the TDI & TDO are connected for forming a chain. As you can observe, every JTAG compliant IC includes 4- pins which are used for JTAG where 3-pins are inputs and 4th pin is output. The fifth pin like TRST is optional. Usually, the JTAG pins are not shared for other purposes.

By using the Joint Test Action Group, all the ICs utilize boundary testing which the original reason is created by JTAG. At present, the usage of this protocol has been extended to permit different things like configuring FPGAs & after that JTAG is used in the FPGA core for debugging purposes.

JTAG Architecture

The JTAG architecture is shown below. In this architecture, all the signals in between the core logic of the device & the pins are interrupted through a serial scan path called BSR or Boundary Scan Register. This BSR includes various boundary scan ‘cells’. Generally, these boundary scan cells are not visible but they can be used to set or read values within test mode from the device pins.

The JTAG interface called a TAP or Test Access Port uses different signals for supporting the boundary scan operation like TCK, TMS, TDI, TDO, and TRST.

• The TCK or Test Clock signal simply synchronizes the inside operations of a state machine.
• TMS or Test Mode Select signal is sampled at the increasing edge of a test clock signal for deciding the next state.
• TDI or Test Data In signal signifies the shifted data into the test device otherwise programming logic. Once the inside state machine is in the right state then it is sampled at the increasing edge of TCK.
• TDO or Test Data Out signal signifies the shifted out data of the test device otherwise programming logic. Once the inside state machine is in the right state then it is valid on the decreasing edge of TCK
• TRST or Test Reset is an optional pin that is used to reset the state machine of the TAP controller.

TAP Controller

The test access point in the architecture of JTAG is composed of a TAP controller, an instruction register & test data registers. This controller includes the testing state machine which is accountable for reading the TMS & TCK signals. Here, the data i/p pin is simply used to load data into the boundary cells in between the IC core & physical pins, and also load data into one of the data registers or into the instruction register. The data o/p pin is used for reading data from either the registers or boundary cells.

The state machine of the TAP controller is controlled by the TMS and it is clocked by TCK. State machine uses two paths for signifying two different modes like instruction mode & data mode.

Registers

There are two kinds of registers available within boundary scan. Every compliant device includes min two or above data registers & one instruction register.

Instruction Register

The instruction register is used to hold the current instruction. So its data is used by the TAP controller to decide what to execute with signals that are obtained. Most frequently, the instruction register data will describe to which of the data registers signals must be passed.

Data Registers

The data registers are available in three types the BSR (Boundary Scan Register), the BYPASS & the ID CODES register. And also, other data registers may be there, however they are not necessary as an element of the JTAG standard.

Boundary Scan Register (BSR)

BSR is the main testing data register that is used to shift data from and to the device I/O pins.

BYPASS

Bypass is a single-bit register used to pass data from TDI – TDO. So it allows additional devices within a circuit to be tested by minimum overhead.

ID CODES

This type of data register includes the ID code as well as the revision number for the device. So this data allows the device to be connected to its BSDL (Boundary Scan Description Language) file. This file included the Boundary Scan configuration details for the device.

The working of JTAG is, initially, the instruction mode is chosen where one of the states in this mode ‘path’ lets the operator clock within an instruction by TDI. After that., the state machine develops until it rearranges. The next step for most instructions is to choose the data mode. So in this mode, the data is loaded through TDI to read from TDO. For TDI & TDO, the data paths will be arranged in compliance with the instruction that has been clocked in. Once the read/write operation is done, again the state machine develops to the reset state.

Difference between JTAG Vs UART

The difference between JTAG and UART includes the following.

JTAG Protocol Analyzer

JTAG Protocol Analyzer like PGY-JTAG-EX-PD is one kind of Protocol Analyzer including some features to capture & debug communication in between host & design under test. This type of analyzer is the leading instrument that allows the test & design engineers for testing the particular designs of JTAG for its specifications through arranging the PGY-JTAG-EX-PD like Master or Slave to generate JTAG traffic & decoding the decode packets of the Joint Test Action Group protocol.

Features

The features of the JTAG protocol analyzer include the following.

• It supports up to 25MH of JTAG frequencies.
• It generates JTAG traffic & protocol decode for the Bus simultaneously.
• It has JTAG Master Capability.
• Variable JTAG Data speeds & Duty cycle.
• User-defined TDI & TCK Delays.
• Host computer USB 2.0 or 3.0 interface.
• Error Analysis within Protocol Decode
• Protocol decoded bus timing diagram.
• Continuous protocol data streaming to the host computer for providing a large buffer.
• Protocol activity list.
• At various speeds, an exercise script can be written for combining multiple data frame generation.

Timing Diagram

The timing diagram of the JTAG protocol is shown below. In the following diagram, the TDO pin remains within the high impedance condition except for during a shift-IR/ shift-DR controller state.
In the shift-IR & Shift-DR controller conditions, the TDO pin is updated on the decreasing edge of TCK through Target and sampled on the increasing edge of TCK through Host.

Both the TDI & TMS pins are simply sampled on the increasing edge of TCK through Target. Updated on the decreasing edge otherwise TCK through Host.

Applications

The JTAG applications include the following.

• Joint Test Action Group is frequently used in Processors for providing the right of entry to their emulation or debug functions.
• All CPLDs & FPGAs use this as an interface to give access to their programming functions.
• It is used for PCBs testing without physical access
• It is used for board-level manufacturing tests.

Thus, this is all about an overview of JTAG – pin configuration, working with applications. The industry standard JTAG is used for design verification as well as PCB testing after manufacture. Here is a question for you, JTAG stands for?